Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jun-2025 12:28:23 4464
FPDL13_DWMZ_200600 20-Jun-2025 12:53:50 3842
SXDL31_DWAV_190800 19-Jun-2025 07:54:59 7028
SXDL31_DWAV_191800 19-Jun-2025 17:10:10 5150
SXDL31_DWAV_200800 20-Jun-2025 07:42:34 11159
SXDL31_DWAV_201800 20-Jun-2025 16:41:25 6949
SXDL31_DWAV_LATEST 20-Jun-2025 16:41:25 6949
SXDL33_DWAV_190000 19-Jun-2025 10:37:36 10783
SXDL33_DWAV_200000 20-Jun-2025 10:57:04 7604
SXDL33_DWAV_LATEST 20-Jun-2025 10:57:04 7604
ber01-FWDL39_DWMS_191230-2506191230-dsw--0-ia5 19-Jun-2025 11:36:43 1603
ber01-FWDL39_DWMS_191230_COR-2506191230-dsw--0-ia5 19-Jun-2025 12:29:36 1607
ber01-FWDL39_DWMS_201230-2506201230-dsw--0-ia5 20-Jun-2025 11:52:30 1582
ber01-VHDL13_DWEH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:28:12 2115
ber01-VHDL13_DWEH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:28:11 1893
ber01-VHDL13_DWEH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:28:12 2141
ber01-VHDL13_DWEH_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:58:11 2371
ber01-VHDL13_DWEH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:28:11 2371
ber01-VHDL13_DWEH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:28:11 2223
ber01-VHDL13_DWEH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:28:12 2590
ber01-VHDL13_DWEH_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:58:06 2537
ber01-VHDL13_DWHG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:10 2414
ber01-VHDL13_DWHG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:05 2274
ber01-VHDL13_DWHG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:08 2597
ber01-VHDL13_DWHG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:12 2597
ber01-VHDL13_DWHG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2867
ber01-VHDL13_DWHG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:08 2660
ber01-VHDL13_DWHG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:07 2856
ber01-VHDL13_DWHG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:12 2670
ber01-VHDL13_DWHH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:10 2603
ber01-VHDL13_DWHH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:05 2236
ber01-VHDL13_DWHH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:08 2537
ber01-VHDL13_DWHH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:12 2537
ber01-VHDL13_DWHH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2587
ber01-VHDL13_DWHH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:08 2425
ber01-VHDL13_DWHH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:07 2697
ber01-VHDL13_DWHH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:12 2514
ber01-VHDL13_DWLG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:03 1360
ber01-VHDL13_DWLG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1280
ber01-VHDL13_DWLG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1563
ber01-VHDL13_DWLG_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:59:56 1591
ber01-VHDL13_DWLG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:01 1638
ber01-VHDL13_DWLG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:08 1568
ber01-VHDL13_DWLG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 1890
ber01-VHDL13_DWLG_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:59:56 1879
ber01-VHDL13_DWLH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:03 1332
ber01-VHDL13_DWLH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1270
ber01-VHDL13_DWLH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1545
ber01-VHDL13_DWLH_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:59:56 1588
ber01-VHDL13_DWLH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:01 1638
ber01-VHDL13_DWLH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:08 1647
ber01-VHDL13_DWLH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2023
ber01-VHDL13_DWLH_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:59:56 2012
ber01-VHDL13_DWLI_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:03 1362
ber01-VHDL13_DWLI_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1282
ber01-VHDL13_DWLI_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1565
ber01-VHDL13_DWLI_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:59:56 1597
ber01-VHDL13_DWLI_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:01 1644
ber01-VHDL13_DWLI_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:08 1628
ber01-VHDL13_DWLI_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 1949
ber01-VHDL13_DWLI_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:59:56 1941
ber01-VHDL13_DWMG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:10 2039
ber01-VHDL13_DWMG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1781
ber01-VHDL13_DWMG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 2064
ber01-VHDL13_DWMG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 1994
ber01-VHDL13_DWMG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2221
ber01-VHDL13_DWMG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 2057
ber01-VHDL13_DWMG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2343
ber01-VHDL13_DWMG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2361
ber01-VHDL13_DWMO_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:10 1894
ber01-VHDL13_DWMO_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1651
ber01-VHDL13_DWMO_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1835
ber01-VHDL13_DWMO_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 1828
ber01-VHDL13_DWMO_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2171
ber01-VHDL13_DWMO_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 2029
ber01-VHDL13_DWMO_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2335
ber01-VHDL13_DWMO_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2353
ber01-VHDL13_DWMP_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:10 2012
ber01-VHDL13_DWMP_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1847
ber01-VHDL13_DWMP_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 2239
ber01-VHDL13_DWMP_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 2159
ber01-VHDL13_DWMP_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2312
ber01-VHDL13_DWMP_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 2143
ber01-VHDL13_DWMP_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2371
ber01-VHDL13_DWMP_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2389
ber01-VHDL13_DWOG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 3039
ber01-VHDL13_DWOG_191700-2506191700-dsw--0-ia5 19-Jun-2025 18:00:01 2442
ber01-VHDL13_DWOG_200300-2506200300-dsw--0-ia5 20-Jun-2025 03:00:01 3138
ber01-VHDL13_DWOG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:01 3312
ber01-VHDL13_DWOG_201700-2506201700-dsw--0-ia5 20-Jun-2025 18:00:02 3029
ber01-VHDL13_DWOG_210300-2506210300-dsw--0-ia5 21-Jun-2025 03:00:06 3601
ber01-VHDL13_DWOH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:28:12 2202
ber01-VHDL13_DWOH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:28:11 1905
ber01-VHDL13_DWOH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:28:06 2190
ber01-VHDL13_DWOH_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:58:07 2365
ber01-VHDL13_DWOH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:28:11 2365
ber01-VHDL13_DWOH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:28:07 2223
ber01-VHDL13_DWOH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:28:06 2584
ber01-VHDL13_DWOH_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:58:12 2525
ber01-VHDL13_DWOI_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:28:08 2085
ber01-VHDL13_DWOI_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:28:06 1846
ber01-VHDL13_DWOI_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:28:12 2197
ber01-VHDL13_DWOI_200400-2506200400-dsw--0-ia5 20-Jun-2025 04:58:11 2457
ber01-VHDL13_DWOI_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:28:07 2463
ber01-VHDL13_DWOI_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:28:07 2346
ber01-VHDL13_DWOI_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:28:12 2743
ber01-VHDL13_DWOI_210400-2506210400-dsw--0-ia5 21-Jun-2025 04:58:12 2683
ber01-VHDL13_DWON_191340-2506191340-dsw--0-ia5 19-Jun-2025 13:40:21 3029
ber01-VHDL13_DWON_191709-2506191709-dsw--0-ia5 19-Jun-2025 17:09:42 2570
ber01-VHDL13_DWON_191714-2506191714-dsw--0-ia5 19-Jun-2025 17:14:37 2620
ber01-VHDL13_DWON_191811-2506191811-dsw--0-ia5 19-Jun-2025 18:11:42 2618
ber01-VHDL13_DWON_192048-2506192048-dsw--0-ia5 19-Jun-2025 20:48:45 2618
ber01-VHDL13_DWON_192216-2506192216-dsw--0-ia5 19-Jun-2025 22:16:23 3276
ber01-VHDL13_DWON_200003-2506200003-dsw--0-ia5 20-Jun-2025 00:03:36 3388
ber01-VHDL13_DWON_200132-2506200132-dsw--0-ia5 20-Jun-2025 01:32:41 3364
ber01-VHDL13_DWON_200235-2506200235-dsw--0-ia5 20-Jun-2025 02:35:55 3364
ber01-VHDL13_DWON_200529-2506200529-dsw--0-ia5 20-Jun-2025 05:29:57 3200
ber01-VHDL13_DWON_200610-2506200610-dsw--0-ia5 20-Jun-2025 06:10:42 3542
ber01-VHDL13_DWON_201227-2506201227-dsw--0-ia5 20-Jun-2025 12:27:27 3397
ber01-VHDL13_DWON_201421-2506201421-dsw--0-ia5 20-Jun-2025 14:21:11 3389
ber01-VHDL13_DWON_201754-2506201754-dsw--0-ia5 20-Jun-2025 17:54:47 3187
ber01-VHDL13_DWON_202005-2506202005-dsw--0-ia5 20-Jun-2025 20:05:32 3187
ber01-VHDL13_DWON_202233-2506202233-dsw--0-ia5 20-Jun-2025 22:33:56 3493
ber01-VHDL13_DWON_210247-2506210247-dsw--0-ia5 21-Jun-2025 02:47:08 3493
ber01-VHDL13_DWON_210257-2506210257-dsw--0-ia5 21-Jun-2025 02:57:23 3471
ber01-VHDL13_DWON_210526-2506210526-dsw--0-ia5 21-Jun-2025 05:26:31 4019
ber01-VHDL13_DWPG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1493
ber01-VHDL13_DWPG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1234
ber01-VHDL13_DWPG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1465
ber01-VHDL13_DWPG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 1546
ber01-VHDL13_DWPG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 1592
ber01-VHDL13_DWPG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 1561
ber01-VHDL13_DWPG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 1813
ber01-VHDL13_DWPG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 1810
ber01-VHDL13_DWPH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1776
ber01-VHDL13_DWPH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1409
ber01-VHDL13_DWPH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 1639
ber01-VHDL13_DWPH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 1835
ber01-VHDL13_DWPH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 1883
ber01-VHDL13_DWPH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 1704
ber01-VHDL13_DWPH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2048
ber01-VHDL13_DWPH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2044
ber01-VHDL13_DWSG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1977
ber01-VHDL13_DWSG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1711
ber01-VHDL13_DWSG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:30:02 2129
ber01-VHDL13_DWSG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:08 2129
ber01-VHDL13_DWSG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:01 2252
ber01-VHDL13_DWSG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 2019
ber01-VHDL13_DWSG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:30:02 2135
ber01-VHDL13_DWSG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2202
ber01-VHDL13_DWSN_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1514
ber01-VHDL13_DWSN_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1666
ber01-VHDL13_DWSN_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:08 2001
ber01-VHDL13_DWSN_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2018
ber01-VHDL13_DWSN_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 1889
ber01-VHDL13_DWSN_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2100
ber01-VHDL13_DWSO_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1677
ber01-VHDL13_DWSO_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1617
ber01-VHDL13_DWSO_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:08 2032
ber01-VHDL13_DWSO_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 2132
ber01-VHDL13_DWSO_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 1901
ber01-VHDL13_DWSO_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2117
ber01-VHDL13_DWSP_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:30:01 1585
ber01-VHDL13_DWSP_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:30:02 1592
ber01-VHDL13_DWSP_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:08 2014
ber01-VHDL13_DWSP_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:30:08 1996
ber01-VHDL13_DWSP_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:30:02 1875
ber01-VHDL13_DWSP_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2084
ber01-VHDL17_DWOG_191200-2506191200-dsw--0-ia5 19-Jun-2025 11:41:05 3601
ber01-VHDL17_DWOG_201200-2506201200-dsw--0-ia5 20-Jun-2025 11:19:37 2666
swis2-VHDL20_DWEG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:07 2381
swis2-VHDL20_DWEG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 2090
swis2-VHDL20_DWEG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2322
swis2-VHDL20_DWEG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:15:02 2573
swis2-VHDL20_DWEG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2544
swis2-VHDL20_DWEG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 2408
swis2-VHDL20_DWEG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2716
swis2-VHDL20_DWEG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:15:07 2733
swis2-VHDL20_DWEH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:07 2293
swis2-VHDL20_DWEH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:06 2093
swis2-VHDL20_DWEH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2305
swis2-VHDL20_DWEH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:15:11 2549
swis2-VHDL20_DWEH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:06 2549
swis2-VHDL20_DWEH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:07 2423
swis2-VHDL20_DWEH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:09 2754
swis2-VHDL20_DWEH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:15:11 2715
swis2-VHDL20_DWEI_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:07 2264
swis2-VHDL20_DWEI_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 2031
swis2-VHDL20_DWEI_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2330
swis2-VHDL20_DWEI_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:15:11 2642
swis2-VHDL20_DWEI_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2642
swis2-VHDL20_DWEI_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 2531
swis2-VHDL20_DWEI_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2876
swis2-VHDL20_DWEI_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:15:11 2868
swis2-VHDL20_DWHG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2597
swis2-VHDL20_DWHG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:06 2457
swis2-VHDL20_DWHG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2783
swis2-VHDL20_DWHG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:12 2780
swis2-VHDL20_DWHG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 3050
swis2-VHDL20_DWHG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 2843
swis2-VHDL20_DWHG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:09 3042
swis2-VHDL20_DWHG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:12 2853
swis2-VHDL20_DWHH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2789
swis2-VHDL20_DWHH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:06 2422
swis2-VHDL20_DWHH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2723
swis2-VHDL20_DWHH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:12 2723
swis2-VHDL20_DWHH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2773
swis2-VHDL20_DWHH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 2611
swis2-VHDL20_DWHH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:09 2883
swis2-VHDL20_DWHH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:12 2700
swis2-VHDL20_DWLG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 1584
swis2-VHDL20_DWLG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1501
swis2-VHDL20_DWLG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 1784
swis2-VHDL20_DWLG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:26 1812
swis2-VHDL20_DWLG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 1862
swis2-VHDL20_DWLG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 1789
swis2-VHDL20_DWLG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2111
swis2-VHDL20_DWLG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:22 2100
swis2-VHDL20_DWLH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 1553
swis2-VHDL20_DWLH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1491
swis2-VHDL20_DWLH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 1766
swis2-VHDL20_DWLH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:26 1809
swis2-VHDL20_DWLH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 1859
swis2-VHDL20_DWLH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 1868
swis2-VHDL20_DWLH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2244
swis2-VHDL20_DWLH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:22 2233
swis2-VHDL20_DWLI_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 1583
swis2-VHDL20_DWLI_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1503
swis2-VHDL20_DWLI_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 1786
swis2-VHDL20_DWLI_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:26 1815
swis2-VHDL20_DWLI_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 1865
swis2-VHDL20_DWLI_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 1849
swis2-VHDL20_DWLI_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2170
swis2-VHDL20_DWLI_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:22 2159
swis2-VHDL20_DWMG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2250
swis2-VHDL20_DWMG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1992
swis2-VHDL20_DWMG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2275
swis2-VHDL20_DWMG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 2205
swis2-VHDL20_DWMG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2432
swis2-VHDL20_DWMG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:07 2268
swis2-VHDL20_DWMG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2556
swis2-VHDL20_DWMG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2572
swis2-VHDL20_DWMO_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2106
swis2-VHDL20_DWMO_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1863
swis2-VHDL20_DWMO_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2050
swis2-VHDL20_DWMO_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 2043
swis2-VHDL20_DWMO_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2383
swis2-VHDL20_DWMO_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:07 2241
swis2-VHDL20_DWMO_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2550
swis2-VHDL20_DWMO_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2568
swis2-VHDL20_DWMP_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2224
swis2-VHDL20_DWMP_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 2046
swis2-VHDL20_DWMP_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2451
swis2-VHDL20_DWMP_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 2371
swis2-VHDL20_DWMP_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2524
swis2-VHDL20_DWMP_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:07 2344
swis2-VHDL20_DWMP_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2583
swis2-VHDL20_DWMP_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2601
swis2-VHDL20_DWPG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 1690
swis2-VHDL20_DWPG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1431
swis2-VHDL20_DWPG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 1662
swis2-VHDL20_DWPG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 1741
swis2-VHDL20_DWPG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 1789
swis2-VHDL20_DWPG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 1758
swis2-VHDL20_DWPG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2010
swis2-VHDL20_DWPG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2005
swis2-VHDL20_DWPH_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 1973
swis2-VHDL20_DWPH_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1606
swis2-VHDL20_DWPH_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 1836
swis2-VHDL20_DWPH_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:00:02 2032
swis2-VHDL20_DWPH_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2080
swis2-VHDL20_DWPH_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 1901
swis2-VHDL20_DWPH_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2245
swis2-VHDL20_DWPH_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:00:08 2241
swis2-VHDL20_DWSG_190800-2506190800-dsw--0-ia5 19-Jun-2025 08:45:05 2208
swis2-VHDL20_DWSG_191300-2506191300-dsw--0-ia5 19-Jun-2025 13:45:07 2111
swis2-VHDL20_DWSG_191800-2506191800-dsw--0-ia5 19-Jun-2025 18:45:02 1943
swis2-VHDL20_DWSG_200200-2506200200-dsw--0-ia5 20-Jun-2025 02:45:08 2364
swis2-VHDL20_DWSG_200400-2506200400-dsw--0-ia5 20-Jun-2025 05:15:02 2361
swis2-VHDL20_DWSG_200800-2506200800-dsw--0-ia5 20-Jun-2025 08:45:02 2482
swis2-VHDL20_DWSG_201300-2506201300-dsw--0-ia5 20-Jun-2025 13:45:04 2446
swis2-VHDL20_DWSG_201800-2506201800-dsw--0-ia5 20-Jun-2025 18:45:01 2251
swis2-VHDL20_DWSG_210200-2506210200-dsw--0-ia5 21-Jun-2025 02:45:04 2369
swis2-VHDL20_DWSG_210400-2506210400-dsw--0-ia5 21-Jun-2025 05:15:01 2433
wst04-VHDL20_DWEG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:10 263536
wst04-VHDL20_DWEG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:11 262864
wst04-VHDL20_DWEG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:08 263508
wst04-VHDL20_DWEG_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:15:06 263975
wst04-VHDL20_DWEG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:06 263961
wst04-VHDL20_DWEG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:12 265357
wst04-VHDL20_DWEG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:12 265014
wst04-VHDL20_DWEG_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:15:11 265629
wst04-VHDL20_DWEH_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:07 259174
wst04-VHDL20_DWEH_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:11 263826
wst04-VHDL20_DWEH_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:08 265027
wst04-VHDL20_DWEH_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:15:06 265388
wst04-VHDL20_DWEH_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:06 265294
wst04-VHDL20_DWEH_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:12 265503
wst04-VHDL20_DWEH_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:12 265718
wst04-VHDL20_DWEH_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:15:07 265351
wst04-VHDL20_DWEI_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:10 369708
wst04-VHDL20_DWEI_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:17 365559
wst04-VHDL20_DWEI_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:18 366740
wst04-VHDL20_DWEI_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:15:11 366579
wst04-VHDL20_DWEI_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:12 366608
wst04-VHDL20_DWEI_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:16 367316
wst04-VHDL20_DWEI_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:16 367979
wst04-VHDL20_DWEI_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:15:07 367652
wst04-VHDL20_DWHG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:22 360515
wst04-VHDL20_DWHG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:17 361387
wst04-VHDL20_DWHG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:15 362061
wst04-VHDL20_DWHG_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:06 362048
wst04-VHDL20_DWHG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:21 362683
wst04-VHDL20_DWHG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:22 364859
wst04-VHDL20_DWHG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:16 365207
wst04-VHDL20_DWHG_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:12 364905
wst04-VHDL20_DWHH_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:22 350144
wst04-VHDL20_DWHH_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:21 353852
wst04-VHDL20_DWHH_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:10 354453
wst04-VHDL20_DWHH_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:12 354488
wst04-VHDL20_DWHH_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:16 354618
wst04-VHDL20_DWHH_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:16 351199
wst04-VHDL20_DWHH_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:16 351855
wst04-VHDL20_DWHH_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:08 351447
wst04-VHDL20_DWLG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:40:26 345984
wst04-VHDL20_DWLG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:40:27 355815
wst04-VHDL20_DWLG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:40:26 355938
wst04-VHDL20_DWLG_200400-2506200400-omedes--0.pdf 20-Jun-2025 04:59:36 356458
wst04-VHDL20_DWLG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:40:26 356154
wst04-VHDL20_DWLG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:40:27 360143
wst04-VHDL20_DWLG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:40:30 360696
wst04-VHDL20_DWLG_210400-2506210400-omedes--0.pdf 21-Jun-2025 04:59:37 360911
wst04-VHDL20_DWLH_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:40:16 351828
wst04-VHDL20_DWLH_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:40:17 353571
wst04-VHDL20_DWLH_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:40:18 354068
wst04-VHDL20_DWLH_200400-2506200400-omedes--0.pdf 20-Jun-2025 04:59:36 354215
wst04-VHDL20_DWLH_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:40:16 354274
wst04-VHDL20_DWLH_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:40:17 357447
wst04-VHDL20_DWLH_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:40:22 357690
wst04-VHDL20_DWLH_210400-2506210400-omedes--0.pdf 21-Jun-2025 04:59:37 357883
wst04-VHDL20_DWLI_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:40:37 356349
wst04-VHDL20_DWLI_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:40:37 359422
wst04-VHDL20_DWLI_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:40:35 359531
wst04-VHDL20_DWLI_200400-2506200400-omedes--0.pdf 20-Jun-2025 04:59:36 360071
wst04-VHDL20_DWLI_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:40:36 360122
wst04-VHDL20_DWLI_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:40:37 362512
wst04-VHDL20_DWLI_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:40:37 363074
wst04-VHDL20_DWLI_210400-2506210400-omedes--0.pdf 21-Jun-2025 04:59:37 363318
wst04-VHDL20_DWMG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:16 573660
wst04-VHDL20_DWMG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:17 572907
wst04-VHDL20_DWMG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:15 574035
wst04-VHDL20_DWMG_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:12 573426
wst04-VHDL20_DWMG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:16 573211
wst04-VHDL20_DWMG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:12 569208
wst04-VHDL20_DWMG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:08 569922
wst04-VHDL20_DWMG_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:12 569339
wst04-VHDL20_DWMO_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:16 461410
wst04-VHDL20_DWMO_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:11 462818
wst04-VHDL20_DWMO_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:08 463796
wst04-VHDL20_DWMO_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:12 464138
wst04-VHDL20_DWMO_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:12 463089
wst04-VHDL20_DWMO_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:12 459204
wst04-VHDL20_DWMO_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:08 460351
wst04-VHDL20_DWMO_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:12 460801
wst04-VHDL20_DWMP_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:16 579481
wst04-VHDL20_DWMP_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:17 580987
wst04-VHDL20_DWMP_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:10 581322
wst04-VHDL20_DWMP_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:12 581445
wst04-VHDL20_DWMP_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:16 581598
wst04-VHDL20_DWMP_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:16 583069
wst04-VHDL20_DWMP_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:12 583296
wst04-VHDL20_DWMP_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:12 583537
wst04-VHDL20_DWPG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:12 402426
wst04-VHDL20_DWPG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:06 358376
wst04-VHDL20_DWPG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:15 358866
wst04-VHDL20_DWPG_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:06 359034
wst04-VHDL20_DWPG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:12 403276
wst04-VHDL20_DWPG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:07 359542
wst04-VHDL20_DWPG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:16 359775
wst04-VHDL20_DWPG_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:08 359990
wst04-VHDL20_DWPH_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:07 304376
wst04-VHDL20_DWPH_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:06 308537
wst04-VHDL20_DWPH_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:12 264491
wst04-VHDL20_DWPH_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:00:06 264783
wst04-VHDL20_DWPH_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:06 309398
wst04-VHDL20_DWPH_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:07 307948
wst04-VHDL20_DWPH_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:12 263560
wst04-VHDL20_DWPH_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:00:08 263803
wst04-VHDL20_DWSG_190800-2506190800-omedes--0.pdf 19-Jun-2025 08:45:16 371603
wst04-VHDL20_DWSG_191300-2506191300-omedes--0.pdf 19-Jun-2025 13:45:07 376247
wst04-VHDL20_DWSG_191800-2506191800-omedes--0.pdf 19-Jun-2025 18:45:11 375278
wst04-VHDL20_DWSG_200200-2506200200-omedes--0.pdf 20-Jun-2025 02:45:22 375769
wst04-VHDL20_DWSG_200400-2506200400-omedes--0.pdf 20-Jun-2025 05:15:08 375890
wst04-VHDL20_DWSG_200800-2506200800-omedes--0.pdf 20-Jun-2025 08:45:16 375790
wst04-VHDL20_DWSG_201300-2506201300-omedes--0.pdf 20-Jun-2025 13:45:06 369818
wst04-VHDL20_DWSG_201800-2506201800-omedes--0.pdf 20-Jun-2025 18:45:16 369607
wst04-VHDL20_DWSG_210200-2506210200-omedes--0.pdf 21-Jun-2025 02:45:22 369843
wst04-VHDL20_DWSG_210400-2506210400-omedes--0.pdf 21-Jun-2025 05:15:07 370665