Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Aug-2025 12:27:09 2932
FPDL13_DWMZ_240600 24-Aug-2025 11:06:55 3674
SXDL31_DWAV_230800 23-Aug-2025 07:31:19 7206
SXDL31_DWAV_231800 23-Aug-2025 16:05:18 5386
SXDL31_DWAV_240800 24-Aug-2025 07:43:59 6265
SXDL31_DWAV_241800 24-Aug-2025 16:32:59 4306
SXDL31_DWAV_LATEST 24-Aug-2025 16:32:59 4306
SXDL33_DWAV_230000 23-Aug-2025 10:36:21 11535
SXDL33_DWAV_240000 24-Aug-2025 09:29:44 5608
SXDL33_DWAV_LATEST 24-Aug-2025 09:29:44 5608
ber01-FWDL39_DWMS_231230-2508231230-dsw--0-ia5 23-Aug-2025 12:02:51 1264
ber01-FWDL39_DWMS_241230-2508241230-dsw--0-ia5 24-Aug-2025 12:05:31 1277
ber01-VHDL13_DWEH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:28:17 2297
ber01-VHDL13_DWEH_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:58:15 2337
ber01-VHDL13_DWEH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:28:17 2296
ber01-VHDL13_DWEH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:28:16 1909
ber01-VHDL13_DWEH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:28:17 2292
ber01-VHDL13_DWEH_240400-2508240400-dsw--0-ia5 24-Aug-2025 04:58:12 2346
ber01-VHDL13_DWEH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:28:17 2354
ber01-VHDL13_DWEH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:28:16 2199
ber01-VHDL13_DWHG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:06 2811
ber01-VHDL13_DWHG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:12 2809
ber01-VHDL13_DWHG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:10 3004
ber01-VHDL13_DWHG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:08 2312
ber01-VHDL13_DWHG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 2415
ber01-VHDL13_DWHG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:12 2415
ber01-VHDL13_DWHG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:05 2562
ber01-VHDL13_DWHG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:09 2271
ber01-VHDL13_DWHH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:06 2788
ber01-VHDL13_DWHH_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:12 2787
ber01-VHDL13_DWHH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:10 3016
ber01-VHDL13_DWHH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:08 2513
ber01-VHDL13_DWHH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 2637
ber01-VHDL13_DWHH_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:12 2637
ber01-VHDL13_DWHH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:05 2779
ber01-VHDL13_DWHH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:09 2400
ber01-VHDL13_DWLG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:06 2058
ber01-VHDL13_DWLG_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:59:56 1900
ber01-VHDL13_DWLG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:01 1882
ber01-VHDL13_DWLG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1552
ber01-VHDL13_DWLG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 1834
ber01-VHDL13_DWLG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:01 1729
ber01-VHDL13_DWLG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 1781
ber01-VHDL13_DWLG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 1596
ber01-VHDL13_DWLH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:06 1958
ber01-VHDL13_DWLH_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:59:56 1897
ber01-VHDL13_DWLH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:01 1855
ber01-VHDL13_DWLH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1537
ber01-VHDL13_DWLH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 1860
ber01-VHDL13_DWLH_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:01 1798
ber01-VHDL13_DWLH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 1795
ber01-VHDL13_DWLH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 1611
ber01-VHDL13_DWLI_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:06 1757
ber01-VHDL13_DWLI_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:59:56 1929
ber01-VHDL13_DWLI_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:01 1884
ber01-VHDL13_DWLI_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1576
ber01-VHDL13_DWLI_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:01 1825
ber01-VHDL13_DWLI_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:01 1735
ber01-VHDL13_DWLI_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 1684
ber01-VHDL13_DWLI_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 1555
ber01-VHDL13_DWMG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 1925
ber01-VHDL13_DWMG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:02 1925
ber01-VHDL13_DWMG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:03 2088
ber01-VHDL13_DWMG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1804
ber01-VHDL13_DWMG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:01 1945
ber01-VHDL13_DWMG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:06 2079
ber01-VHDL13_DWMG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 2128
ber01-VHDL13_DWMG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:09 2045
ber01-VHDL13_DWMO_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 2098
ber01-VHDL13_DWMO_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:02 2098
ber01-VHDL13_DWMO_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:03 2118
ber01-VHDL13_DWMO_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1906
ber01-VHDL13_DWMO_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:01 2128
ber01-VHDL13_DWMO_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:06 2128
ber01-VHDL13_DWMO_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 2228
ber01-VHDL13_DWMO_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:09 2128
ber01-VHDL13_DWMP_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 2027
ber01-VHDL13_DWMP_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:02 2027
ber01-VHDL13_DWMP_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:03 2077
ber01-VHDL13_DWMP_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1847
ber01-VHDL13_DWMP_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:01 2014
ber01-VHDL13_DWMP_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:06 2012
ber01-VHDL13_DWMP_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 2139
ber01-VHDL13_DWMP_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:09 2159
ber01-VHDL13_DWOG_230300-2508230300-dsw--0-ia5 23-Aug-2025 03:00:03 4218
ber01-VHDL13_DWOG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:01 4155
ber01-VHDL13_DWOG_230800_COR-2508230800-dsw--0-ia5 23-Aug-2025 13:07:03 4138
ber01-VHDL13_DWOG_231700-2508231700-dsw--0-ia5 23-Aug-2025 18:00:02 3227
ber01-VHDL13_DWOG_240300-2508240300-dsw--0-ia5 24-Aug-2025 03:00:04 3514
ber01-VHDL13_DWOG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 3416
ber01-VHDL13_DWOG_241700-2508241700-dsw--0-ia5 24-Aug-2025 18:00:06 3316
ber01-VHDL13_DWOG_250300_COR-2508250300-dsw--0-ia5 25-Aug-2025 00:55:56 3714
ber01-VHDL13_DWOH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:28:17 2180
ber01-VHDL13_DWOH_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:58:15 2193
ber01-VHDL13_DWOH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:28:17 2188
ber01-VHDL13_DWOH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:28:12 1822
ber01-VHDL13_DWOH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:28:11 2098
ber01-VHDL13_DWOH_240400-2508240400-dsw--0-ia5 24-Aug-2025 04:58:16 2095
ber01-VHDL13_DWOH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:28:17 2078
ber01-VHDL13_DWOH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:28:16 1966
ber01-VHDL13_DWOI_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:28:11 2123
ber01-VHDL13_DWOI_230400-2508230400-dsw--0-ia5 23-Aug-2025 04:58:12 2095
ber01-VHDL13_DWOI_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:28:11 2094
ber01-VHDL13_DWOI_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:28:12 1716
ber01-VHDL13_DWOI_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:28:11 2043
ber01-VHDL13_DWOI_240400-2508240400-dsw--0-ia5 24-Aug-2025 04:58:16 2034
ber01-VHDL13_DWOI_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:28:13 2073
ber01-VHDL13_DWOI_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:28:12 1993
ber01-VHDL13_DWON_230255-2508230255-dsw--0-ia5 23-Aug-2025 02:56:02 3694
ber01-VHDL13_DWON_230507-2508230507-dsw--0-ia5 23-Aug-2025 05:07:52 3552
ber01-VHDL13_DWON_230635-2508230635-dsw--0-ia5 23-Aug-2025 06:35:45 4150
ber01-VHDL13_DWON_230742-2508230742-dsw--0-ia5 23-Aug-2025 07:42:51 4150
ber01-VHDL13_DWON_230854-2508230854-dsw--0-ia5 23-Aug-2025 08:54:35 4150
ber01-VHDL13_DWON_231252-2508231252-dsw--0-ia5 23-Aug-2025 12:52:33 4171
ber01-VHDL13_DWON_231306-2508231306-dsw--0-ia5 23-Aug-2025 13:06:47 4171
ber01-VHDL13_DWON_231445-2508231445-dsw--0-ia5 23-Aug-2025 14:45:31 4115
ber01-VHDL13_DWON_231700-2508231700-dsw--0-ia5 23-Aug-2025 17:00:32 3449
ber01-VHDL13_DWON_231912-2508231912-dsw--0-ia5 23-Aug-2025 19:12:37 3513
ber01-VHDL13_DWON_240032-2508240032-dsw--0-ia5 24-Aug-2025 00:32:05 3919
ber01-VHDL13_DWON_240249-2508240249-dsw--0-ia5 24-Aug-2025 02:49:31 3793
ber01-VHDL13_DWON_240454-2508240454-dsw--0-ia5 24-Aug-2025 04:54:37 3659
ber01-VHDL13_DWON_240731-2508240731-dsw--0-ia5 24-Aug-2025 07:31:13 3659
ber01-VHDL13_DWON_240737-2508240737-dsw--0-ia5 24-Aug-2025 07:37:40 3659
ber01-VHDL13_DWON_240745-2508240745-dsw--0-ia5 24-Aug-2025 07:45:37 3654
ber01-VHDL13_DWON_241200-2508241200-dsw--0-ia5 24-Aug-2025 12:00:27 3654
ber01-VHDL13_DWON_241206-2508241206-dsw--0-ia5 24-Aug-2025 12:06:51 3654
ber01-VHDL13_DWON_241407-2508241407-dsw--0-ia5 24-Aug-2025 14:07:27 3479
ber01-VHDL13_DWON_241419-2508241419-dsw--0-ia5 24-Aug-2025 14:19:02 3441
ber01-VHDL13_DWON_241447-2508241447-dsw--0-ia5 24-Aug-2025 14:48:02 3441
ber01-VHDL13_DWON_241635-2508241635-dsw--0-ia5 24-Aug-2025 16:35:11 3441
ber01-VHDL13_DWON_242123-2508242123-dsw--0-ia5 24-Aug-2025 21:23:23 2986
ber01-VHDL13_DWON_250054-2508250054-dsw--0-ia5 25-Aug-2025 00:54:56 3674
ber01-VHDL13_DWPG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 2197
ber01-VHDL13_DWPG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:02 2174
ber01-VHDL13_DWPG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:10 2116
ber01-VHDL13_DWPG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:06 1656
ber01-VHDL13_DWPG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 1947
ber01-VHDL13_DWPG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:03 1873
ber01-VHDL13_DWPG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 1848
ber01-VHDL13_DWPG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 1659
ber01-VHDL13_DWPH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 2261
ber01-VHDL13_DWPH_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:02 2391
ber01-VHDL13_DWPH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:10 2426
ber01-VHDL13_DWPH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:06 1890
ber01-VHDL13_DWPH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 2336
ber01-VHDL13_DWPH_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:03 2145
ber01-VHDL13_DWPH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 2125
ber01-VHDL13_DWPH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 1879
ber01-VHDL13_DWSG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:30:02 1868
ber01-VHDL13_DWSG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:08 1947
ber01-VHDL13_DWSG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:30:01 1948
ber01-VHDL13_DWSG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:30:02 1731
ber01-VHDL13_DWSG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:30:07 2275
ber01-VHDL13_DWSG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:08 2334
ber01-VHDL13_DWSG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:30:02 2322
ber01-VHDL13_DWSG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:30:01 2076
ber01-VHDL17_DWOG_231200-2508231200-dsw--0-ia5 23-Aug-2025 11:07:26 3218
ber01-VHDL17_DWOG_241200-2508241200-dsw--0-ia5 24-Aug-2025 11:52:01 1931
swis2-VHDL20_DWEG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:04 2312
swis2-VHDL20_DWEG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:15:06 2401
swis2-VHDL20_DWEG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:05 2367
swis2-VHDL20_DWEG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:01 2007
swis2-VHDL20_DWEG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:45:09 2230
swis2-VHDL20_DWEG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:15:04 2303
swis2-VHDL20_DWEG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:45:06 2257
swis2-VHDL20_DWEG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:45:04 2151
swis2-VHDL20_DWEH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:12 2461
swis2-VHDL20_DWEH_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:15:16 2515
swis2-VHDL20_DWEH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:11 2474
swis2-VHDL20_DWEH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:12 2109
swis2-VHDL20_DWEH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:45:12 2456
swis2-VHDL20_DWEH_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:15:16 2524
swis2-VHDL20_DWEH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:45:12 2532
swis2-VHDL20_DWEH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:45:18 2398
swis2-VHDL20_DWEI_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:06 2256
swis2-VHDL20_DWEI_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:15:16 2280
swis2-VHDL20_DWEI_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:05 2273
swis2-VHDL20_DWEI_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:01 1901
swis2-VHDL20_DWEI_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:45:09 2176
swis2-VHDL20_DWEI_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:15:16 2219
swis2-VHDL20_DWEI_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:45:06 2252
swis2-VHDL20_DWEI_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:45:04 2178
swis2-VHDL20_DWHG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:04 2997
swis2-VHDL20_DWHG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:12 2992
swis2-VHDL20_DWHG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:09 3187
swis2-VHDL20_DWHG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:01 2495
swis2-VHDL20_DWHG_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:45:09 2601
swis2-VHDL20_DWHG_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:12 2598
swis2-VHDL20_DWHG_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:45:04 2745
swis2-VHDL20_DWHG_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:45:06 2454
swis2-VHDL20_DWHH_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:04 2974
swis2-VHDL20_DWHH_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:12 2973
swis2-VHDL20_DWHH_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:09 3202
swis2-VHDL20_DWHH_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:01 2699
swis2-VHDL20_DWHH_240200-2508240200-dsw--0-ia5 24-Aug-2025 02:45:09 2823
swis2-VHDL20_DWHH_240400-2508240400-dsw--0-ia5 24-Aug-2025 05:00:12 2823
swis2-VHDL20_DWHH_240800-2508240800-dsw--0-ia5 24-Aug-2025 08:45:04 2965
swis2-VHDL20_DWHH_241800-2508241800-dsw--0-ia5 24-Aug-2025 18:45:06 2586
swis2-VHDL20_DWLG_230200-2508230200-dsw--0-ia5 23-Aug-2025 02:45:04 2279
swis2-VHDL20_DWLG_230400-2508230400-dsw--0-ia5 23-Aug-2025 05:00:26 2121
swis2-VHDL20_DWLG_230800-2508230800-dsw--0-ia5 23-Aug-2025 08:45:09 2106
swis2-VHDL20_DWLG_231800-2508231800-dsw--0-ia5 23-Aug-2025 18:45:01 1773
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