Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Feb-2026 14:16:28 3615
SXDL31_DWAV_031800 03-Feb-2026 18:20:54 5626
SXDL31_DWAV_040800 04-Feb-2026 08:39:40 10901
SXDL31_DWAV_041800 04-Feb-2026 17:26:55 13116
SXDL31_DWAV_050800 05-Feb-2026 09:17:58 8187
SXDL31_DWAV_LATEST 05-Feb-2026 09:17:58 8187
SXDL33_DWAV_040000 04-Feb-2026 11:23:19 11978
SXDL33_DWAV_050000 05-Feb-2026 11:25:34 7692
SXDL33_DWAV_LATEST 05-Feb-2026 11:25:34 7692
ber01-FWDL39_DWMS_041230-2602041230-dsw--0-ia5 04-Feb-2026 11:48:36 2187
ber01-FWDL39_DWMS_051230-2602051230-dsw--0-ia5 05-Feb-2026 12:01:31 1752
ber01-VHDL13_DWEH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:28:16 3451
ber01-VHDL13_DWEH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:28:11 3220
ber01-VHDL13_DWEH_040400-2602040400-dsw--0-ia5 04-Feb-2026 05:58:17 3014
ber01-VHDL13_DWEH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:28:16 3132
ber01-VHDL13_DWEH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:28:16 2721
ber01-VHDL13_DWEH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:28:17 3173
ber01-VHDL13_DWEH_050400-2602050400-dsw--0-ia5 05-Feb-2026 05:58:16 3503
ber01-VHDL13_DWEH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:17 3731
ber01-VHDL13_DWHG_030800_COR-2602030800-dsw--0-ia5 03-Feb-2026 16:37:36 5188
ber01-VHDL13_DWHG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 4602
ber01-VHDL13_DWHG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 3743
ber01-VHDL13_DWHG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3743
ber01-VHDL13_DWHG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 3617
ber01-VHDL13_DWHG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:06 3081
ber01-VHDL13_DWHG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:06 3408
ber01-VHDL13_DWHG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:06 3408
ber01-VHDL13_DWHG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3498
ber01-VHDL13_DWHH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 3739
ber01-VHDL13_DWHH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 2790
ber01-VHDL13_DWHH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 2818
ber01-VHDL13_DWHH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 3441
ber01-VHDL13_DWHH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:06 2830
ber01-VHDL13_DWHH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:06 3037
ber01-VHDL13_DWHH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:06 3037
ber01-VHDL13_DWHH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3073
ber01-VHDL13_DWLG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 2541
ber01-VHDL13_DWLG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 2600
ber01-VHDL13_DWLG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:02 2737
ber01-VHDL13_DWLG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 2533
ber01-VHDL13_DWLG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2226
ber01-VHDL13_DWLG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2460
ber01-VHDL13_DWLG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2395
ber01-VHDL13_DWLG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2520
ber01-VHDL13_DWLH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 2505
ber01-VHDL13_DWLH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:02 2478
ber01-VHDL13_DWLH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:02 2524
ber01-VHDL13_DWLH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 2474
ber01-VHDL13_DWLH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2378
ber01-VHDL13_DWLH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2719
ber01-VHDL13_DWLH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2502
ber01-VHDL13_DWLH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2574
ber01-VHDL13_DWLI_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 2720
ber01-VHDL13_DWLI_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 2361
ber01-VHDL13_DWLI_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:02 2355
ber01-VHDL13_DWLI_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 2505
ber01-VHDL13_DWLI_040800_COR-2602040800-dsw--0-ia5 04-Feb-2026 10:57:01 2609
ber01-VHDL13_DWLI_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2247
ber01-VHDL13_DWLI_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2291
ber01-VHDL13_DWLI_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2427
ber01-VHDL13_DWLI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2572
ber01-VHDL13_DWMG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:02 3576
ber01-VHDL13_DWMG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:02 3276
ber01-VHDL13_DWMG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3366
ber01-VHDL13_DWMG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:03 3466
ber01-VHDL13_DWMG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2964
ber01-VHDL13_DWMG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2917
ber01-VHDL13_DWMG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2927
ber01-VHDL13_DWMG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3247
ber01-VHDL13_DWMO_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:02 3461
ber01-VHDL13_DWMO_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:02 3128
ber01-VHDL13_DWMO_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3119
ber01-VHDL13_DWMO_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:03 3472
ber01-VHDL13_DWMO_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2750
ber01-VHDL13_DWMO_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2965
ber01-VHDL13_DWMO_050200_COR-2602050200-dsw--0-ia5 05-Feb-2026 03:36:55 2815
ber01-VHDL13_DWMO_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2823
ber01-VHDL13_DWMO_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3122
ber01-VHDL13_DWMP_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:02 3177
ber01-VHDL13_DWMP_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:02 3318
ber01-VHDL13_DWMP_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3310
ber01-VHDL13_DWMP_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:03 3204
ber01-VHDL13_DWMP_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2980
ber01-VHDL13_DWMP_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2967
ber01-VHDL13_DWMP_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2976
ber01-VHDL13_DWMP_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3198
ber01-VHDL13_DWOG_031700-2602031700-dsw--0-ia5 03-Feb-2026 19:00:01 5840
ber01-VHDL13_DWOG_040300-2602040300-dsw--0-ia5 04-Feb-2026 04:00:11 5671
ber01-VHDL13_DWOG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:03 5394
ber01-VHDL13_DWOG_041700-2602041700-dsw--0-ia5 04-Feb-2026 19:00:01 5004
ber01-VHDL13_DWOG_050300-2602050300-dsw--0-ia5 05-Feb-2026 04:00:02 5629
ber01-VHDL13_DWOG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:51:11 6258
ber01-VHDL13_DWOH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:28:12 3272
ber01-VHDL13_DWOH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:28:11 2980
ber01-VHDL13_DWOH_040400-2602040400-dsw--0-ia5 04-Feb-2026 05:58:17 3002
ber01-VHDL13_DWOH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:28:16 2910
ber01-VHDL13_DWOH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:28:16 2803
ber01-VHDL13_DWOH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:28:11 2671
ber01-VHDL13_DWOH_050400-2602050400-dsw--0-ia5 05-Feb-2026 05:58:12 2963
ber01-VHDL13_DWOH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:11 3183
ber01-VHDL13_DWOI_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:28:12 2844
ber01-VHDL13_DWOI_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:28:11 2885
ber01-VHDL13_DWOI_040400-2602040400-dsw--0-ia5 04-Feb-2026 05:58:11 2981
ber01-VHDL13_DWOI_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:28:12 2622
ber01-VHDL13_DWOI_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:28:12 2610
ber01-VHDL13_DWOI_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:28:11 2897
ber01-VHDL13_DWOI_050400-2602050400-dsw--0-ia5 05-Feb-2026 05:58:16 2873
ber01-VHDL13_DWOI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:11 2785
ber01-VHDL13_DWON_031539-2602031539-dsw--0-ia5 03-Feb-2026 15:39:21 4174
ber01-VHDL13_DWON_031831-2602031831-dsw--0-ia5 03-Feb-2026 18:31:55 4174
ber01-VHDL13_DWON_032015-2602032015-dsw--0-ia5 03-Feb-2026 20:15:56 4190
ber01-VHDL13_DWON_040018-2602040018-dsw--0-ia5 04-Feb-2026 00:18:46 4039
ber01-VHDL13_DWON_040353-2602040353-dsw--0-ia5 04-Feb-2026 03:53:42 4039
ber01-VHDL13_DWON_040354-2602040354-dsw--0-ia5 04-Feb-2026 03:54:42 4039
ber01-VHDL13_DWON_040623-2602040623-dsw--0-ia5 04-Feb-2026 06:23:32 4763
ber01-VHDL13_DWON_040648-2602040648-dsw--0-ia5 04-Feb-2026 06:48:46 4763
ber01-VHDL13_DWON_040906-2602040906-dsw--0-ia5 04-Feb-2026 09:06:22 4647
ber01-VHDL13_DWON_040958-2602040958-dsw--0-ia5 04-Feb-2026 09:58:36 4647
ber01-VHDL13_DWON_041557-2602041557-dsw--0-ia5 04-Feb-2026 15:57:21 4333
ber01-VHDL13_DWON_041715-2602041715-dsw--0-ia5 04-Feb-2026 17:15:47 4124
ber01-VHDL13_DWON_041747-2602041747-dsw--0-ia5 04-Feb-2026 17:47:11 4124
ber01-VHDL13_DWON_042042-2602042042-dsw--0-ia5 04-Feb-2026 20:42:55 4275
ber01-VHDL13_DWON_042116-2602042116-dsw--0-ia5 04-Feb-2026 21:17:02 4275
ber01-VHDL13_DWON_042342-2602042342-dsw--0-ia5 04-Feb-2026 23:42:48 4259
ber01-VHDL13_DWON_050015-2602050015-dsw--0-ia5 05-Feb-2026 00:15:46 4239
ber01-VHDL13_DWON_050016-2602050016-dsw--0-ia5 05-Feb-2026 00:16:11 4239
ber01-VHDL13_DWON_050023-2602050023-dsw--0-ia5 05-Feb-2026 00:23:57 4239
ber01-VHDL13_DWON_050626-2602050626-dsw--0-ia5 05-Feb-2026 06:26:41 4308
ber01-VHDL13_DWON_050652-2602050652-dsw--0-ia5 05-Feb-2026 06:52:37 4296
ber01-VHDL13_DWON_050925-2602050925-dsw--0-ia5 05-Feb-2026 09:25:26 4296
ber01-VHDL13_DWON_050949-2602050949-dsw--0-ia5 05-Feb-2026 09:49:29 4296
ber01-VHDL13_DWPG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 3210
ber01-VHDL13_DWPG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 3198
ber01-VHDL13_DWPG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:02 3266
ber01-VHDL13_DWPG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 3003
ber01-VHDL13_DWPG_040800_COR-2602040800-dsw--0-ia5 04-Feb-2026 12:26:27 3098
ber01-VHDL13_DWPG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 3088
ber01-VHDL13_DWPG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 3039
ber01-VHDL13_DWPG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 2879
ber01-VHDL13_DWPG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2798
ber01-VHDL13_DWPH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:07 3244
ber01-VHDL13_DWPH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:06 3266
ber01-VHDL13_DWPH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:02 3308
ber01-VHDL13_DWPH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:07 3269
ber01-VHDL13_DWPH_040800_COR-2602040800-dsw--0-ia5 04-Feb-2026 12:26:41 3505
ber01-VHDL13_DWPH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 3525
ber01-VHDL13_DWPH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 3839
ber01-VHDL13_DWPH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:02 3470
ber01-VHDL13_DWPH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3324
ber01-VHDL13_DWSG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:30:02 2525
ber01-VHDL13_DWSG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:30:02 2779
ber01-VHDL13_DWSG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 2861
ber01-VHDL13_DWSG_040400_COR-2602040400-dsw--0-ia5 04-Feb-2026 07:12:57 2758
ber01-VHDL13_DWSG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:30:03 2755
ber01-VHDL13_DWSG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:30:02 2653
ber01-VHDL13_DWSG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:30:02 2788
ber01-VHDL13_DWSG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:06 2789
ber01-VHDL13_DWSG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 2789
ber01-VHDL13_DWSG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 11:11:01 2761
ber01-VHDL17_DWOG_041200-2602041200-dsw--0-ia5 04-Feb-2026 12:53:21 5118
ber01-VHDL17_DWOG_051200-2602051200-dsw--0-ia5 05-Feb-2026 12:46:53 4228
swis2-VHDL20_DWEG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3809
swis2-VHDL20_DWEG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3441
swis2-VHDL20_DWEG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:02 3386
swis2-VHDL20_DWEG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3534
swis2-VHDL20_DWEG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3358
swis2-VHDL20_DWEG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3062
swis2-VHDL20_DWEG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3344
swis2-VHDL20_DWEG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3889
swis2-VHDL20_DWEH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3937
swis2-VHDL20_DWEH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3811
swis2-VHDL20_DWEH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:02 3412
swis2-VHDL20_DWEH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 4061
swis2-VHDL20_DWEH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3271
swis2-VHDL20_DWEH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3796
swis2-VHDL20_DWEH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 4192
swis2-VHDL20_DWEH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4637
swis2-VHDL20_DWEI_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3388
swis2-VHDL20_DWEI_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3444
swis2-VHDL20_DWEI_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:02 3401
swis2-VHDL20_DWEI_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3355
swis2-VHDL20_DWEI_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3030
swis2-VHDL20_DWEI_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3255
swis2-VHDL20_DWEI_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3366
swis2-VHDL20_DWEI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3453
swis2-VHDL20_DWHG_030800_COR-2602030800-dsw--0-ia5 03-Feb-2026 16:36:52 6301
swis2-VHDL20_DWHG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 4785
swis2-VHDL20_DWHG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 3929
swis2-VHDL20_DWHG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3926
swis2-VHDL20_DWHG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 4440
swis2-VHDL20_DWHG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 3264
swis2-VHDL20_DWHG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:06 3594
swis2-VHDL20_DWHG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:06 3591
swis2-VHDL20_DWHG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4354
swis2-VHDL20_DWHH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3925
swis2-VHDL20_DWHH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 2976
swis2-VHDL20_DWHH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:06 3004
swis2-VHDL20_DWHH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 4270
swis2-VHDL20_DWHH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3016
swis2-VHDL20_DWHH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:06 3223
swis2-VHDL20_DWHH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:06 3223
swis2-VHDL20_DWHH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4002
swis2-VHDL20_DWLG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 2947
swis2-VHDL20_DWLG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 3006
swis2-VHDL20_DWLG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:12 3228
swis2-VHDL20_DWLG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3205
swis2-VHDL20_DWLG_041800-2602041800-dsw--0-ia5 04-Feb-2026 21:52:24 2494
swis2-VHDL20_DWLG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 2899
swis2-VHDL20_DWLG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:12 2827
swis2-VHDL20_DWLG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3118
swis2-VHDL20_DWLH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 2917
swis2-VHDL20_DWLH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 2890
swis2-VHDL20_DWLH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:12 2973
swis2-VHDL20_DWLH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3106
swis2-VHDL20_DWLH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 2826
swis2-VHDL20_DWLH_041800_COR-2602041800-dsw--0-ia5 04-Feb-2026 21:50:25 2806
swis2-VHDL20_DWLH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3167
swis2-VHDL20_DWLH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:12 2929
swis2-VHDL20_DWLH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3184
swis2-VHDL20_DWLI_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3128
swis2-VHDL20_DWLI_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 2748
swis2-VHDL20_DWLI_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:12 2738
swis2-VHDL20_DWLI_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3116
swis2-VHDL20_DWLI_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 2662
swis2-VHDL20_DWLI_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 2706
swis2-VHDL20_DWLI_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:12 2815
swis2-VHDL20_DWLI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3171
swis2-VHDL20_DWMG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 4092
swis2-VHDL20_DWMG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:06 3894
swis2-VHDL20_DWMG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 4226
swis2-VHDL20_DWMG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3499
swis2-VHDL20_DWMG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3440
swis2-VHDL20_DWMG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3349
swis2-VHDL20_DWMG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 4040
swis2-VHDL20_DWMO_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3981
swis2-VHDL20_DWMO_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3640
swis2-VHDL20_DWMO_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:06 3640
swis2-VHDL20_DWMO_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 4243
swis2-VHDL20_DWMO_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3281
swis2-VHDL20_DWMO_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3359
swis2-VHDL20_DWMO_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3252
swis2-VHDL20_DWMO_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3926
swis2-VHDL20_DWMP_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3623
swis2-VHDL20_DWMP_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3748
swis2-VHDL20_DWMP_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:06 3800
swis2-VHDL20_DWMP_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 3972
swis2-VHDL20_DWMP_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:06 3508
swis2-VHDL20_DWMP_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3501
swis2-VHDL20_DWMP_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3401
swis2-VHDL20_DWMP_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 4006
swis2-VHDL20_DWPG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 3932
swis2-VHDL20_DWPG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 3617
swis2-VHDL20_DWPG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:12 3767
swis2-VHDL20_DWPG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 3904
swis2-VHDL20_DWPG_040800_COR-2602040800-dsw--0-ia5 04-Feb-2026 12:28:02 3908
swis2-VHDL20_DWPG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 3893
swis2-VHDL20_DWPG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3512
swis2-VHDL20_DWPG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:12 3412
swis2-VHDL20_DWPG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3383
swis2-VHDL20_DWPH_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:01 4042
swis2-VHDL20_DWPH_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:06 3762
swis2-VHDL20_DWPH_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:00:12 3807
swis2-VHDL20_DWPH_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:07 4248
swis2-VHDL20_DWPH_040800_COR-2602040800-dsw--0-ia5 04-Feb-2026 12:28:17 4300
swis2-VHDL20_DWPH_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 4300
swis2-VHDL20_DWPH_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 4377
swis2-VHDL20_DWPH_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:00:12 3952
swis2-VHDL20_DWPH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3860
swis2-VHDL20_DWSG_031300-2602031300-dsw--0-ia5 03-Feb-2026 14:45:06 3215
swis2-VHDL20_DWSG_031800-2602031800-dsw--0-ia5 03-Feb-2026 19:45:07 2931
swis2-VHDL20_DWSG_040200-2602040200-dsw--0-ia5 04-Feb-2026 03:45:02 3265
swis2-VHDL20_DWSG_040400-2602040400-dsw--0-ia5 04-Feb-2026 06:15:02 3268
swis2-VHDL20_DWSG_040400_COR-2602040400-dsw--0-ia5 04-Feb-2026 07:12:57 3124
swis2-VHDL20_DWSG_040800-2602040800-dsw--0-ia5 04-Feb-2026 09:45:03 3277
swis2-VHDL20_DWSG_041300-2602041300-dsw--0-ia5 04-Feb-2026 14:45:08 3149
swis2-VHDL20_DWSG_041800-2602041800-dsw--0-ia5 04-Feb-2026 19:45:01 3021
swis2-VHDL20_DWSG_050200-2602050200-dsw--0-ia5 05-Feb-2026 03:45:02 3147
swis2-VHDL20_DWSG_050400-2602050400-dsw--0-ia5 05-Feb-2026 06:15:07 3229
swis2-VHDL20_DWSG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3375
swis2-VHDL20_DWSG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 11:11:01 3292
wst04-VHDL20_DWEG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:13 232562
wst04-VHDL20_DWEG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:16 233192
wst04-VHDL20_DWEG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:12 232674
wst04-VHDL20_DWEG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:11 230874
wst04-VHDL20_DWEG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:12 229972
wst04-VHDL20_DWEG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:12 229712
wst04-VHDL20_DWEG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:21 230048
wst04-VHDL20_DWEG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 227461
wst04-VHDL20_DWEH_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:13 235754
wst04-VHDL20_DWEH_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:16 236529
wst04-VHDL20_DWEH_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:16 235973
wst04-VHDL20_DWEH_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:11 229563
wst04-VHDL20_DWEH_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:12 228623
wst04-VHDL20_DWEH_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:12 230295
wst04-VHDL20_DWEH_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:21 229578
wst04-VHDL20_DWEH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 229213
wst04-VHDL20_DWEI_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:13 333846
wst04-VHDL20_DWEI_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:16 334582
wst04-VHDL20_DWEI_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:16 335093
wst04-VHDL20_DWEI_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:11 327110
wst04-VHDL20_DWEI_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:12 326414
wst04-VHDL20_DWEI_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:12 326745
wst04-VHDL20_DWEI_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:21 326233
wst04-VHDL20_DWEI_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:16 319010
wst04-VHDL20_DWHG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:21 307439
wst04-VHDL20_DWHG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:22 306343
wst04-VHDL20_DWHG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:12 306219
wst04-VHDL20_DWHG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:27 308366
wst04-VHDL20_DWHG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:16 305497
wst04-VHDL20_DWHG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:22 305753
wst04-VHDL20_DWHG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:12 305747
wst04-VHDL20_DWHG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:23 301317
wst04-VHDL20_DWHH_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:21 298676
wst04-VHDL20_DWHH_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:22 298529
wst04-VHDL20_DWHH_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:12 298593
wst04-VHDL20_DWHH_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:27 295103
wst04-VHDL20_DWHH_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:22 293996
wst04-VHDL20_DWHH_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:22 293869
wst04-VHDL20_DWHH_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:12 293909
wst04-VHDL20_DWHH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:23 291444
wst04-VHDL20_DWLG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:25 306245
wst04-VHDL20_DWLG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:20 306191
wst04-VHDL20_DWLG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:42 305611
wst04-VHDL20_DWLG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:31 302883
wst04-VHDL20_DWLG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:26 302373
wst04-VHDL20_DWLG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:26 302304
wst04-VHDL20_DWLG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:42 301905
wst04-VHDL20_DWLG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 302732
wst04-VHDL20_DWLH_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:21 300907
wst04-VHDL20_DWLH_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:26 300768
wst04-VHDL20_DWLH_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:42 300034
wst04-VHDL20_DWLH_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:31 300031
wst04-VHDL20_DWLH_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:22 299473
wst04-VHDL20_DWLH_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:26 300117
wst04-VHDL20_DWLH_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:42 299240
wst04-VHDL20_DWLH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 297751
wst04-VHDL20_DWLI_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:21 304903
wst04-VHDL20_DWLI_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:26 304781
wst04-VHDL20_DWLI_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:42 304003
wst04-VHDL20_DWLI_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:27 293045
wst04-VHDL20_DWLI_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:22 292698
wst04-VHDL20_DWLI_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:20 292287
wst04-VHDL20_DWLI_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:42 292047
wst04-VHDL20_DWLI_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 289297
wst04-VHDL20_DWMG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:17 521722
wst04-VHDL20_DWMG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:16 521677
wst04-VHDL20_DWMG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:16 521669
wst04-VHDL20_DWMG_040400_COR-2602040400-omedes-..> 04-Feb-2026 07:12:27 521669
wst04-VHDL20_DWMG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:22 504911
wst04-VHDL20_DWMG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:16 504594
wst04-VHDL20_DWMG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:16 504218
wst04-VHDL20_DWMG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:17 504588
wst04-VHDL20_DWMG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 502337
wst04-VHDL20_DWMO_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:17 408155
wst04-VHDL20_DWMO_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:12 407774
wst04-VHDL20_DWMO_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:16 408208
wst04-VHDL20_DWMO_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:22 400031
wst04-VHDL20_DWMO_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:16 399143
wst04-VHDL20_DWMO_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:16 399571
wst04-VHDL20_DWMO_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:17 400008
wst04-VHDL20_DWMO_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 400823
wst04-VHDL20_DWMP_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:17 553344
wst04-VHDL20_DWMP_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:12 552375
wst04-VHDL20_DWMP_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:22 553472
wst04-VHDL20_DWMP_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:22 541228
wst04-VHDL20_DWMP_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:16 540482
wst04-VHDL20_DWMP_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:16 539412
wst04-VHDL20_DWMP_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:21 541028
wst04-VHDL20_DWMP_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 537755
wst04-VHDL20_DWPG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:25 311706
wst04-VHDL20_DWPG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:20 310964
wst04-VHDL20_DWPG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:32 311288
wst04-VHDL20_DWPG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:31 354862
wst04-VHDL20_DWPG_040800_COR-2602040800-omedes-..> 04-Feb-2026 12:27:25 354862
wst04-VHDL20_DWPG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:26 310307
wst04-VHDL20_DWPG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:26 310130
wst04-VHDL20_DWPG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:30 309677
wst04-VHDL20_DWPG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 351205
wst04-VHDL20_DWPH_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:21 268377
wst04-VHDL20_DWPH_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:20 223089
wst04-VHDL20_DWPH_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:00:32 223853
wst04-VHDL20_DWPH_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:27 263467
wst04-VHDL20_DWPH_040800_COR-2602040800-omedes-..> 04-Feb-2026 12:27:45 263506
wst04-VHDL20_DWPH_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:22 263696
wst04-VHDL20_DWPH_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:20 219415
wst04-VHDL20_DWPH_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:00:30 218746
wst04-VHDL20_DWPH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 268838
wst04-VHDL20_DWSG_031300-2602031300-omedes--0.pdf 03-Feb-2026 14:45:13 340055
wst04-VHDL20_DWSG_031800-2602031800-omedes--0.pdf 03-Feb-2026 19:45:11 339537
wst04-VHDL20_DWSG_040200-2602040200-omedes--0.pdf 04-Feb-2026 03:45:12 339004
wst04-VHDL20_DWSG_040400-2602040400-omedes--0.pdf 04-Feb-2026 06:15:12 339054
wst04-VHDL20_DWSG_040400_COR-2602040400-omedes-..> 04-Feb-2026 07:13:01 339507
wst04-VHDL20_DWSG_040800-2602040800-omedes--0.pdf 04-Feb-2026 09:45:18 339159
wst04-VHDL20_DWSG_041300-2602041300-omedes--0.pdf 04-Feb-2026 14:45:18 339103
wst04-VHDL20_DWSG_041800-2602041800-omedes--0.pdf 04-Feb-2026 19:45:12 338571
wst04-VHDL20_DWSG_050200-2602050200-omedes--0.pdf 05-Feb-2026 03:45:12 338941
wst04-VHDL20_DWSG_050400-2602050400-omedes--0.pdf 05-Feb-2026 06:15:17 338942
wst04-VHDL20_DWSG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 326201
wst04-VHDL20_DWSG_050800_COR-2602050800-omedes-..> 05-Feb-2026 11:11:07 326198