Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-May-2026 12:41:09 4546
FPDL13_DWMZ_140600 14-May-2026 10:12:23 3847
SXDL31_DWAV_130800 13-May-2026 07:22:10 7652
SXDL31_DWAV_131800 13-May-2026 16:19:05 4896
SXDL31_DWAV_140800 14-May-2026 07:08:59 7228
SXDL31_DWAV_141800 14-May-2026 15:18:25 6603
SXDL31_DWAV_LATEST 14-May-2026 15:18:25 6603
SXDL33_DWAV_130000 13-May-2026 09:55:51 10180
SXDL33_DWAV_140000 14-May-2026 10:08:49 7578
SXDL33_DWAV_LATEST 14-May-2026 10:08:49 7578
ber01-FWDL39_DWMS_131230-2605131230-dsw--0-ia5 13-May-2026 11:37:18 2414
ber01-FWDL39_DWMS_141230-2605141230-dsw--0-ia5 14-May-2026 11:07:42 1821
ber01-VHDL13_DWEG_130800-2605130800-dsw--0-ia5 13-May-2026 08:28:22 2889
ber01-VHDL13_DWEG_140800-2605140800-dsw--0-ia5 14-May-2026 08:28:17 2943
ber01-VHDL13_DWEG_140800_COR-2605140800-dsw--0-ia5 14-May-2026 17:55:52 2835
ber01-VHDL13_DWEH_130800-2605130800-dsw--0-ia5 13-May-2026 08:28:22 2968
ber01-VHDL13_DWEH_140800-2605140800-dsw--0-ia5 14-May-2026 08:28:17 3234
ber01-VHDL13_DWEH_140800_COR-2605140800-dsw--0-ia5 14-May-2026 17:56:17 3018
ber01-VHDL13_DWEI_130800-2605130800-dsw--0-ia5 13-May-2026 08:28:16 2895
ber01-VHDL13_DWEI_140800-2605140800-dsw--0-ia5 14-May-2026 08:28:17 3063
ber01-VHDL13_DWEI_140800_COR-2605140800-dsw--0-ia5 14-May-2026 17:56:41 2980
ber01-VHDL13_DWHG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3376
ber01-VHDL13_DWHG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:17 3524
ber01-VHDL13_DWHH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3111
ber01-VHDL13_DWHH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:18 3090
ber01-VHDL13_DWLG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 2869
ber01-VHDL13_DWLG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3216
ber01-VHDL13_DWLH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 2913
ber01-VHDL13_DWLH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3214
ber01-VHDL13_DWLI_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 2825
ber01-VHDL13_DWLI_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3058
ber01-VHDL13_DWMO_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3246
ber01-VHDL13_DWMO_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3369
ber01-VHDL13_DWMP_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3977
ber01-VHDL13_DWMP_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3985
ber01-VHDL13_DWOG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 3887
ber01-VHDL13_DWOG_131700-2605131700-dsw--0-ia5 13-May-2026 18:00:06 3545
ber01-VHDL13_DWOG_140300-2605140300-dsw--0-ia5 14-May-2026 03:00:10 3769
ber01-VHDL13_DWOG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 4070
ber01-VHDL13_DWOG_141700-2605141700-dsw--0-ia5 14-May-2026 18:00:01 3865
ber01-VHDL13_DWOG_150300-2605150300-dsw--0-ia5 15-May-2026 03:00:11 3819
ber01-VHDL13_DWON_130528-2605130528-dsw--0-ia5 13-May-2026 05:28:17 3696
ber01-VHDL13_DWON_130554-2605130554-dsw--0-ia5 13-May-2026 05:54:37 3766
ber01-VHDL13_DWON_130738-2605130738-dsw--0-ia5 13-May-2026 07:38:32 3767
ber01-VHDL13_DWON_130842-2605130842-dsw--0-ia5 13-May-2026 08:42:07 3767
ber01-VHDL13_DWON_131449-2605131449-dsw--0-ia5 13-May-2026 14:50:06 3233
ber01-VHDL13_DWON_131742-2605131742-dsw--0-ia5 13-May-2026 17:42:12 3107
ber01-VHDL13_DWON_132055-2605132055-dsw--0-ia5 13-May-2026 20:55:56 3107
ber01-VHDL13_DWON_132338-2605132338-dsw--0-ia5 13-May-2026 23:38:21 3575
ber01-VHDL13_DWON_132342-2605132342-dsw--0-ia5 13-May-2026 23:42:11 3575
ber01-VHDL13_DWON_140202-2605140202-dsw--0-ia5 14-May-2026 02:02:16 3575
ber01-VHDL13_DWON_140511-2605140511-dsw--0-ia5 14-May-2026 05:11:57 3919
ber01-VHDL13_DWON_140652-2605140652-dsw--0-ia5 14-May-2026 06:52:57 3919
ber01-VHDL13_DWON_140943-2605140943-dsw--0-ia5 14-May-2026 09:43:22 3919
ber01-VHDL13_DWON_141443-2605141443-dsw--0-ia5 14-May-2026 14:43:35 3476
ber01-VHDL13_DWON_141654-2605141654-dsw--0-ia5 14-May-2026 16:54:17 3444
ber01-VHDL13_DWON_141732-2605141732-dsw--0-ia5 14-May-2026 17:32:10 3444
ber01-VHDL13_DWON_141746-2605141746-dsw--0-ia5 14-May-2026 17:46:41 3444
ber01-VHDL13_DWON_150121-2605150121-dsw--0-ia5 15-May-2026 01:21:21 3663
ber01-VHDL13_DWON_150122-2605150122-dsw--0-ia5 15-May-2026 01:22:51 3663
ber01-VHDL13_DWON_150244-2605150244-dsw--0-ia5 15-May-2026 02:44:21 3663
ber01-VHDL13_DWON_150247-2605150247-dsw--0-ia5 15-May-2026 02:47:29 3651
ber01-VHDL13_DWPG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3035
ber01-VHDL13_DWPG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 2865
ber01-VHDL13_DWPH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 3225
ber01-VHDL13_DWPH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3005
ber01-VHDL13_DWSG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 3465
ber01-VHDL13_DWSG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 3102
ber01-VHDL17_DWOG_131200-2605131200-dsw--0-ia5 13-May-2026 11:53:58 2876
ber01-VHDL17_DWOG_141200-2605141200-dsw--0-ia5 14-May-2026 10:59:17 2952
swis2-VHDL20_DWEG_130400-2605130400-dsw--0-ia5 13-May-2026 05:01:17 1210
swis2-VHDL20_DWEG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 1329
swis2-VHDL20_DWEG_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:01 1741
swis2-VHDL20_DWEG_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 1271
swis2-VHDL20_DWEG_140400-2605140400-dsw--0-ia5 14-May-2026 05:01:17 1522
swis2-VHDL20_DWEG_140400_COR-2605140400-dsw--0-ia5 14-May-2026 05:32:12 1529
swis2-VHDL20_DWEG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 1407
swis2-VHDL20_DWEG_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 1558
swis2-VHDL20_DWEG_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:05 1181
swis2-VHDL20_DWEH_130400-2605130400-dsw--0-ia5 13-May-2026 05:01:17 1320
swis2-VHDL20_DWEH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 1433
swis2-VHDL20_DWEH_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:07 1403
swis2-VHDL20_DWEH_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 992
swis2-VHDL20_DWEH_140400-2605140400-dsw--0-ia5 14-May-2026 05:01:17 1168
swis2-VHDL20_DWEH_140400_COR-2605140400-dsw--0-ia5 14-May-2026 05:32:12 1165
swis2-VHDL20_DWEH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 1462
swis2-VHDL20_DWEH_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 1424
swis2-VHDL20_DWEH_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:05 1209
swis2-VHDL20_DWEI_130400-2605130400-dsw--0-ia5 13-May-2026 05:01:17 1303
swis2-VHDL20_DWEI_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 1422
swis2-VHDL20_DWEI_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:01 1762
swis2-VHDL20_DWEI_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 1292
swis2-VHDL20_DWEI_140400-2605140400-dsw--0-ia5 14-May-2026 05:01:17 1491
swis2-VHDL20_DWEI_140400_COR-2605140400-dsw--0-ia5 14-May-2026 05:32:12 1511
swis2-VHDL20_DWEI_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 1415
swis2-VHDL20_DWEI_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 1553
swis2-VHDL20_DWEI_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:05 1176
swis2-VHDL20_DWHG_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:17 1367
swis2-VHDL20_DWHG_130800-2605130800-dsw--0-ia5 13-May-2026 08:45:06 1876
swis2-VHDL20_DWHG_131800-2605131800-dsw--0-ia5 13-May-2026 18:45:06 1772
swis2-VHDL20_DWHG_140200-2605140200-dsw--0-ia5 14-May-2026 02:45:04 1623
swis2-VHDL20_DWHG_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:17 1587
swis2-VHDL20_DWHG_140800-2605140800-dsw--0-ia5 14-May-2026 08:45:08 1715
swis2-VHDL20_DWHG_141800-2605141800-dsw--0-ia5 14-May-2026 18:45:06 1645
swis2-VHDL20_DWHG_150200-2605150200-dsw--0-ia5 15-May-2026 02:45:05 1887
swis2-VHDL20_DWHH_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:17 1249
swis2-VHDL20_DWHH_130800-2605130800-dsw--0-ia5 13-May-2026 08:45:06 1368
swis2-VHDL20_DWHH_131800-2605131800-dsw--0-ia5 13-May-2026 18:45:06 1266
swis2-VHDL20_DWHH_140200-2605140200-dsw--0-ia5 14-May-2026 02:45:04 1240
swis2-VHDL20_DWHH_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:17 1240
swis2-VHDL20_DWHH_140800-2605140800-dsw--0-ia5 14-May-2026 08:45:08 1241
swis2-VHDL20_DWHH_141800-2605141800-dsw--0-ia5 14-May-2026 18:45:06 1395
swis2-VHDL20_DWHH_150200-2605150200-dsw--0-ia5 15-May-2026 02:45:05 1775
swis2-VHDL20_DWLG_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:15 1221
swis2-VHDL20_DWLG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:22 1341
swis2-VHDL20_DWLG_131800-2605131800-dsw--0-ia5 13-May-2026 18:31:00 1240
swis2-VHDL20_DWLG_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:26 1241
swis2-VHDL20_DWLG_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:11 1211
swis2-VHDL20_DWLG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:28 1515
swis2-VHDL20_DWLG_141800-2605141800-dsw--0-ia5 14-May-2026 18:31:04 1247
swis2-VHDL20_DWLG_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:22 1155
swis2-VHDL20_DWLH_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:15 1227
swis2-VHDL20_DWLH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:22 1347
swis2-VHDL20_DWLH_131800-2605131800-dsw--0-ia5 13-May-2026 18:31:00 1246
swis2-VHDL20_DWLH_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:26 1258
swis2-VHDL20_DWLH_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:11 1239
swis2-VHDL20_DWLH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:28 1506
swis2-VHDL20_DWLH_141800-2605141800-dsw--0-ia5 14-May-2026 18:31:04 1243
swis2-VHDL20_DWLH_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:22 1130
swis2-VHDL20_DWLI_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:15 1289
swis2-VHDL20_DWLI_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:22 1409
swis2-VHDL20_DWLI_131800-2605131800-dsw--0-ia5 13-May-2026 18:31:00 1308
swis2-VHDL20_DWLI_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:26 1298
swis2-VHDL20_DWLI_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:11 1352
swis2-VHDL20_DWLI_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:28 1403
swis2-VHDL20_DWLI_141800-2605141800-dsw--0-ia5 14-May-2026 18:31:04 1262
swis2-VHDL20_DWLI_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:22 1141
swis2-VHDL20_DWMO_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:01 1136
swis2-VHDL20_DWMO_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 1764
swis2-VHDL20_DWMO_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:07 1630
swis2-VHDL20_DWMO_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 1233
swis2-VHDL20_DWMO_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:01 1254
swis2-VHDL20_DWMO_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 1423
swis2-VHDL20_DWMO_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 1316
swis2-VHDL20_DWMO_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:03 1121
swis2-VHDL20_DWMP_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:01 1504
swis2-VHDL20_DWMP_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:10 2250
swis2-VHDL20_DWMP_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:07 2237
swis2-VHDL20_DWMP_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 1637
swis2-VHDL20_DWMP_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:01 1854
swis2-VHDL20_DWMP_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 2057
swis2-VHDL20_DWMP_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 2283
swis2-VHDL20_DWMP_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:03 1598
swis2-VHDL20_DWPG_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:15 1127
swis2-VHDL20_DWPG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:22 1250
swis2-VHDL20_DWPG_131800-2605131800-dsw--0-ia5 13-May-2026 18:31:00 1149
swis2-VHDL20_DWPG_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:26 1157
swis2-VHDL20_DWPG_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:11 1190
swis2-VHDL20_DWPG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:28 1399
swis2-VHDL20_DWPG_141800-2605141800-dsw--0-ia5 14-May-2026 18:31:04 1126
swis2-VHDL20_DWPG_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:22 1104
swis2-VHDL20_DWPH_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:15 1127
swis2-VHDL20_DWPH_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:22 1250
swis2-VHDL20_DWPH_131800-2605131800-dsw--0-ia5 13-May-2026 18:31:00 1149
swis2-VHDL20_DWPH_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:26 1194
swis2-VHDL20_DWPH_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:11 1185
swis2-VHDL20_DWPH_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:28 1269
swis2-VHDL20_DWPH_141800-2605141800-dsw--0-ia5 14-May-2026 18:31:04 1165
swis2-VHDL20_DWPH_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:22 1163
swis2-VHDL20_DWSG_130400-2605130400-dsw--0-ia5 13-May-2026 05:00:17 1303
swis2-VHDL20_DWSG_130800-2605130800-dsw--0-ia5 13-May-2026 08:30:04 1385
swis2-VHDL20_DWSG_131800-2605131800-dsw--0-ia5 13-May-2026 18:30:01 1536
swis2-VHDL20_DWSG_140200-2605140200-dsw--0-ia5 14-May-2026 02:30:02 1377
swis2-VHDL20_DWSG_140400-2605140400-dsw--0-ia5 14-May-2026 05:00:17 1390
swis2-VHDL20_DWSG_140800-2605140800-dsw--0-ia5 14-May-2026 08:30:02 1457
swis2-VHDL20_DWSG_141800-2605141800-dsw--0-ia5 14-May-2026 18:30:01 1479
swis2-VHDL20_DWSG_150200-2605150200-dsw--0-ia5 15-May-2026 02:30:03 1155
wst04-VHDL20_DWEG_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:11 234707
wst04-VHDL20_DWEG_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:41 235494
wst04-VHDL20_DWEG_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:11 237775
wst04-VHDL20_DWEG_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:11 237177
wst04-VHDL20_DWEG_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:11 237203
wst04-VHDL20_DWEG_140400_COR-2605140400-omedes-..> 14-May-2026 05:32:23 237220
wst04-VHDL20_DWEG_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:17 237181
wst04-VHDL20_DWEG_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:13 238461
wst04-VHDL20_DWEG_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:11 237367
wst04-VHDL20_DWEH_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:11 235549
wst04-VHDL20_DWEH_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:37 236408
wst04-VHDL20_DWEH_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:11 238173
wst04-VHDL20_DWEH_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:11 237288
wst04-VHDL20_DWEH_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:11 237629
wst04-VHDL20_DWEH_140400_COR-2605140400-omedes-..> 14-May-2026 05:32:23 237633
wst04-VHDL20_DWEH_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:17 238601
wst04-VHDL20_DWEH_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:13 235399
wst04-VHDL20_DWEH_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:11 234663
wst04-VHDL20_DWEI_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:11 335568
wst04-VHDL20_DWEI_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:37 336565
wst04-VHDL20_DWEI_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:17 340041
wst04-VHDL20_DWEI_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:11 339289
wst04-VHDL20_DWEI_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:17 339895
wst04-VHDL20_DWEI_140400_COR-2605140400-omedes-..> 14-May-2026 05:32:23 339935
wst04-VHDL20_DWEI_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:17 339476
wst04-VHDL20_DWEI_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:13 337748
wst04-VHDL20_DWEI_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:11 336494
wst04-VHDL20_DWHG_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:17 346160
wst04-VHDL20_DWHG_130800-2605130800-omedes--0.pdf 13-May-2026 08:45:12 348171
wst04-VHDL20_DWHG_131800-2605131800-omedes--0.pdf 13-May-2026 18:45:12 351363
wst04-VHDL20_DWHG_140200-2605140200-omedes--0.pdf 14-May-2026 02:45:13 350456
wst04-VHDL20_DWHG_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:21 350458
wst04-VHDL20_DWHG_140800-2605140800-omedes--0.pdf 14-May-2026 08:45:16 352228
wst04-VHDL20_DWHG_141800-2605141800-omedes--0.pdf 14-May-2026 18:45:10 339849
wst04-VHDL20_DWHG_150200-2605150200-omedes--0.pdf 15-May-2026 02:45:12 340315
wst04-VHDL20_DWHH_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:17 233141
wst04-VHDL20_DWHH_130800-2605130800-omedes--0.pdf 13-May-2026 08:45:12 338941
wst04-VHDL20_DWHH_131800-2605131800-omedes--0.pdf 13-May-2026 18:45:12 334254
wst04-VHDL20_DWHH_140200-2605140200-omedes--0.pdf 14-May-2026 02:45:13 334031
wst04-VHDL20_DWHH_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:17 229612
wst04-VHDL20_DWHH_140800-2605140800-omedes--0.pdf 14-May-2026 08:45:16 334365
wst04-VHDL20_DWHH_141800-2605141800-omedes--0.pdf 14-May-2026 18:45:10 328454
wst04-VHDL20_DWHH_150200-2605150200-omedes--0.pdf 15-May-2026 02:45:12 329485
wst04-VHDL20_DWLG_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:41 336652
wst04-VHDL20_DWLG_130800-2605130800-omedes--0.pdf 13-May-2026 08:31:02 336897
wst04-VHDL20_DWLG_131800-2605131800-omedes--0.pdf 13-May-2026 18:31:28 342413
wst04-VHDL20_DWLG_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:26 342976
wst04-VHDL20_DWLG_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:41 342664
wst04-VHDL20_DWLG_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:41 342847
wst04-VHDL20_DWLG_141800-2605141800-omedes--0.pdf 14-May-2026 18:31:22 334811
wst04-VHDL20_DWLG_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:22 335122
wst04-VHDL20_DWLH_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:41 336291
wst04-VHDL20_DWLH_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:54 337292
wst04-VHDL20_DWLH_131800-2605131800-omedes--0.pdf 13-May-2026 18:31:22 341604
wst04-VHDL20_DWLH_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:21 342193
wst04-VHDL20_DWLH_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:41 341834
wst04-VHDL20_DWLH_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:52 342024
wst04-VHDL20_DWLH_141800-2605141800-omedes--0.pdf 14-May-2026 18:31:22 338105
wst04-VHDL20_DWLH_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:22 338396
wst04-VHDL20_DWLI_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:41 334169
wst04-VHDL20_DWLI_130800-2605130800-omedes--0.pdf 13-May-2026 08:31:02 379724
wst04-VHDL20_DWLI_131800-2605131800-omedes--0.pdf 13-May-2026 18:31:22 338426
wst04-VHDL20_DWLI_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:21 338481
wst04-VHDL20_DWLI_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:41 338155
wst04-VHDL20_DWLI_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:41 383008
wst04-VHDL20_DWLI_141800-2605141800-omedes--0.pdf 14-May-2026 18:31:22 333480
wst04-VHDL20_DWLI_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:25 333352
wst04-VHDL20_DWMO_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:17 444420
wst04-VHDL20_DWMO_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:50 444470
wst04-VHDL20_DWMO_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:17 350056
wst04-VHDL20_DWMO_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:16 451396
wst04-VHDL20_DWMO_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:11 451307
wst04-VHDL20_DWMO_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:17 451267
wst04-VHDL20_DWMO_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:17 352844
wst04-VHDL20_DWMO_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:16 459065
wst04-VHDL20_DWMP_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:17 550658
wst04-VHDL20_DWMP_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:50 450048
wst04-VHDL20_DWMP_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:17 449836
wst04-VHDL20_DWMP_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:16 550799
wst04-VHDL20_DWMP_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:17 551256
wst04-VHDL20_DWMP_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:22 450236
wst04-VHDL20_DWMP_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:17 453329
wst04-VHDL20_DWMP_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:16 553739
wst04-VHDL20_DWPG_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:31 342171
wst04-VHDL20_DWPG_130800-2605130800-omedes--0.pdf 13-May-2026 08:31:02 386955
wst04-VHDL20_DWPG_131800-2605131800-omedes--0.pdf 13-May-2026 18:31:22 353058
wst04-VHDL20_DWPG_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:21 247732
wst04-VHDL20_DWPG_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:31 353329
wst04-VHDL20_DWPG_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:52 398965
wst04-VHDL20_DWPG_141800-2605141800-omedes--0.pdf 14-May-2026 18:31:31 342168
wst04-VHDL20_DWPG_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:22 241832
wst04-VHDL20_DWPH_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:31 239946
wst04-VHDL20_DWPH_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:54 240141
wst04-VHDL20_DWPH_131800-2605131800-omedes--0.pdf 13-May-2026 18:31:22 243217
wst04-VHDL20_DWPH_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:21 243747
wst04-VHDL20_DWPH_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:31 243467
wst04-VHDL20_DWPH_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:41 244098
wst04-VHDL20_DWPH_141800-2605141800-omedes--0.pdf 14-May-2026 18:31:22 243942
wst04-VHDL20_DWPH_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:22 243934
wst04-VHDL20_DWSG_130400-2605130400-omedes--0.pdf 13-May-2026 05:00:11 337311
wst04-VHDL20_DWSG_130800-2605130800-omedes--0.pdf 13-May-2026 08:30:43 337554
wst04-VHDL20_DWSG_131800-2605131800-omedes--0.pdf 13-May-2026 18:30:17 354636
wst04-VHDL20_DWSG_140200-2605140200-omedes--0.pdf 14-May-2026 02:30:11 353506
wst04-VHDL20_DWSG_140400-2605140400-omedes--0.pdf 14-May-2026 05:00:11 354392
wst04-VHDL20_DWSG_140800-2605140800-omedes--0.pdf 14-May-2026 08:30:18 355247
wst04-VHDL20_DWSG_141800-2605141800-omedes--0.pdf 14-May-2026 18:30:17 346356
wst04-VHDL20_DWSG_150200-2605150200-omedes--0.pdf 15-May-2026 02:30:11 346117